A typical solid-state storage device comprises one or more arrays of storage cells for storing data. Existing semiconductor technologies provide volatile solid-state storage devices suitable for relatively short term storage of data, such as dynamic random access memory (DRAM), or devices for relatively longer term storage of data such as static random access memory (SRAM) or non-volatile flash and electrically erasable programmable read-only memory (EEPROM) devices.
A magnetoresistive storage device has been developed as a new type of non-volatile solid-state storage device. The magnetoresistive solid-state storage device is also known as magnetic random access memory (MRAM device. MRAM devices have relatively low power consumption and relatively fast access times, particularly for data write operations, which render MRAM devices ideally suited for both short term and long term storage applications.
A problem arises in that MRAM devices are subject to physical failure, which can result in an unacceptable loss of stored data. Physical failures within a MRAM device can result from many causes including manufacturing imperfections, internal effects such as noise in a read process, environmental effects such as temperature and surrounding electromagnetic noise, or ageing of the device in use. Failures can generally be classified as either systematic failures or random failures. Systematic failures consistently affect a particular storage cell or a particular group of storage cells. Random failures occur transiently and are not consistently repeatable. Systematic failures can arise as a result of manufacturing imperfections and ageing. Random failures occur in response to internal effects and to external environmental effects.
Currently available manufacturing techniques for MRAM devices are subject to limitations, and as a result, manufacturing yields of acceptable MRAM devices are relatively low. Although better manufacturing techniques are being developed, these tend to increase manufacturing complexity and cost. It is also desirable to increase cell density formed on a substrate such as silicon, but as the density increases, manufacturing tolerances become increasingly difficult to control, leading to higher error rates and lower device yields.
Currently, error correction coding implemented with memory to remedy manufacturing defects affecting memory accuracy is of one pre-determined size regardless of the level of accuracy of the memory or the intended application of the memory. Typically, the one pre-determined size is the most powerful level of ECC available. However, where the actual defect level of the MRAM device is not taken into account, error correction coding with a higher level of correction capability (“power level”) may be installed for use with an MRAM device than is needed to provide an acceptably accurate device. Similarly, where the intended application of the MRAM device is not taken into account prior to installing the error correction coding, error correction coding capable of a higher accuracy level than is necessary for the intended application may be implemented. Use of over-corrective (higher “power level” than necessary) ECC can unnecessarily slow the speed of operations performed by the device with which the ECC is used and requires greater power to run the machine in which the device is installed.